A typical example of the semiconductor memory device is illustrated in FIG. 1 of the drawings and fabricated on a single semiconductor chip 1. The semiconductor memory device largely comprises a plurality of memory cells 2 arranged in rows and columns (which is called as a memory cell array), a redundant memory cells 3 arranged in a plurality of rows, an address buffer circuit 4 associated with a plurality of address terminals 5 and temporary storing address signls, which are used as a row address signal and a column address signal, supplied from an outside source (not shown), a row address decoder circuit 6 operative to decode the row address signal for selecting one of the rows from the memory cell array 2, a redundant decoder unit 7 operative to produce a replacing signal on the basis of the row address signal for causing the row address decoder circuit 6 to be shifted into inactive state and selecting one of the rows from the redundant memory cells 3, and a redundant state detection unit 8 operative to memorize a replacement of the row or rows of the memory cell array 2 with the row or rows of the redundant memory cells 3 for trouble shooting.
The redundant decoder unit 7 is provided with a plurality of redundant decoder circuits 9, 10 and 11 and n-channel type field effect transistors 12, 13 and 14 respectively associated with the redundant decoder circuits 9, 10 and 11, and the n-channel type field effec transistors 12, 13 and 14 are coupled in parallel between a positive voltage source Vcc and the row address decoder circuit 6. Though not shown in the drawings, each of the redundant decoder circuits 9 to 11 has a fuse element which is disconnected when a memory cell of the aarry 2 is rejected as a defective cell and, accordingly, replaced with a redundant memory cell. When a redundant decoder circuit detects the row address assigned to the memory cell of the array 2 replaced with the redundant memory cell, a high level signal is produced by the redundant decoder circuit and the n-channel type filed effect transistor turns on with the high level signal. Then, the n-channel type field effect transistor propagates a replacing signal of the positive voltage level Vcc which is applied to the row decoder circuit 6. With the replacing signal, the row address decoder circuit 6 keeps inactive and, for this reason, does not respond to the row address signal, but one of the redundant word lines is activated for one of the rows of the redundant memory cells, so that data bits are read out from the redundant memory cells coupled to the redundan word line instead of the memory cells of the array 2.
The redundant state detection unit 8 is provided with a replacement memorizing section 12' and an address detecting section 13'. The replacement memorizing section 12' has a series combination of three n-channel type field effect transistors 14', 15 and 16 and a fuse element 17 coupled between a testing terminal 18 and a diagnostic terminal 19 (which further serves as a power supplying terminal), and ech of the n-channel type field effect transistors 14' to 16 has a gate electrode coupled to a source electrode thereof. When at least one memory cell of the array 2 was replaced with a redundant memory cell, the fuse element 17 was destroyed for disconnecting the n-channel type field effect transistor 16 from the diagnostic terminal 19. However, if no defective memory cell is detected during the diagnosis operation, the fuse element 17 can provide a conduction path between the n-channel type field effect transistor 16 and the diagnostic terminal 19. Thus, the replacement memorizing section 12' is capable of memorizing a historical information whether or not a memory cell of the array 2 has been replaced with a redundant memory cell.
Upon the later diagnosis operation, the positive voltage level Vcc is applied to the diagnosis terminal 19, and the testing terminal 18 is supplied with a positive voltage level Va higher than the positive voltage level Vcc by a value slightly larger than the sum of the threshold voltages of the n-channel type field effect transistors 14' to 16. In thi situation, if the fuse element was destroyed to memorize the replacement, no current flows from the testing terminal 18 to the diagnostic terminal 19 because the conducion path is blocked between the n-channel type field effect transistor 16 and the diagnostic terminal 19. On the other hand, no detective memory cell is detected and, accordingly, all of the memory cells of the array 2 are used to store data bits without replacement. A current flows from the testing terminal 18 to the diagnostic terminal 19, because all of the n-channel type field effect transistors 14' to 16 turn on to propagate the voltage level.
The address detecting section 13' is provided with a plurality of detecting circuits 20, 21 and 22 which are equal in number to the redundant decoder circuits 9 to 11, and the detecting circuits 20 to 22 are coupled in parallel between the diagnostic terminal 19 and the n-channel type field effect transistor 16. The detecting circuits 20 to 22 are respectively coupled in parallel to the respective n-channel type field effect transistors 12 to 14 and are respectively activated to provide conduction paths between the n-channel type field effect transistor 16 and the diagnostic terminal 19, respectively, when the replacing signals appear. All of the detecting circuits 20 to 22 are identical in circuit arrangement with one another, so that description is made for the detecting circuit 20 only for the sake of simplicity.
The detecting circuit 20 has an n-channel type field effect transistor 23 coupled between the n-channel type field effect transistor 16 and the diagnostic terminal 19, and a bootstrapping capacitor 24 with two electrodes one of which is coupled to the n-channel type field effect transistor 14 and the other of which is coupled to the gate electrode of the n-channel type field effect transistor 23. The detecting circuit 20 further has an n-channel type field effect transistor 25 coupled between the other electrode of the bootstrapping capacitor 24 and the diagnostic terminal 19. The detecting circuit 20 thus arranged is capable of providing the conduction path between the n-channel type field effect transistor 16 and the diagnostic terminal 19. Namely, when a replacement is memorized in the redundant decoder circuit 11, the redundant decoder circuit 11 allows the n-channel field effect transistor 14 to turn on to produce the replacing signal upon application of the row address signal assigned to the memory cell replaced with the redundant memory cell. As described above, the replacing signal is supplied to not only the row decoder circuit 6 but also the bootstrapping capacitor 24 of the detecting circuit 20. Then, positive charges are accumulated in the one electrode of the bootstrapping capacitor 24. The positive voltage level is supplied from the diagnostic terminal 19 through the n-channel type field effect transistor 25 to the other electrode of the bootstrapping capacitor 24, so that the voltage level at the gate electrode of the n-channel type field effect transistor 23 goes up beyond the positive voltage level Vcc. With the extremely high voltage level, the n-channel field effect transistor 23 fully turns on to propagate the voltage level between the n-channel type field effect transistor 16 and the diagnostic terminal 19. The voltage level between the n-channel type field effect transistor 16 and the diagnostic terminal 19 is slightly higher than the positive voltage level Vcc because of the voltage level Va at the testing terminal 18. Then, a current flows between the testing terminal 18 and the diagnostic terminal 19. However, if no replacing signal is produced by the n-channel type field effect transistor 14, the n-channel type field effect transistor 23 is turned off to block the conduction path. For this reason, no current is detected between the testing terminal 18 and the diagnostic terminal 19. In this way, the row address assigned to the defective memory cell is detected by the curent flowing from the testing terminal 18 and the diagnostic terminal 19.
However, a problem is encountered in the detecting circuit forming part of the redundant state detection unit 8 of the prior-art semiconductor memory device in complexity in circuit arrangement. Namely, each of the detecting circuits 20 to 22 is constituted by the three component elements, which are two n-channel type field effect transistors 23 and 25 and one bootstrapping capacitor 24, so that a large occupation area is consumed to form the address detecting section. If the rows of the redundant memory cells is increased to save the semiconductor memory device from rejection, the above problem becomes serious.